The present invention relates to a method of manufacturing a bipolar transistor semiconductor device reduced in dimensions and increased in speed.
Bipolar transistors have recently been reduced in dimensions beyond the limit of photolithographic technology by the self-aligned technology as disclosed, for example, in Japanese Patent Publication No. 55-27469, Japanese Laid-open Patent No. 56-1556, Japanese Patent Publication No. 57-32511 and Japanese Laid-open Patent No. 60-164356, and characteristics of extremely high speed and high performance are realized.
To illustrate a semiconductor device by a prior art and its manufacturing method, an example of manufacturing method of NPN transistor is shown in FIGS. 3(a) to 3(d).
First, as shown in FIG. 3(a), after forming an N-type collector buried layer 19 on the surface of a P-type silicon substrate 18, an N-type epitaxial layer 20 is formed on the surface of the N-type collector buried layer 19. Next, after forming a LOCOS film 21 for device isolation in a specific region on the surface of the N-type epitaxial layer 20, a P+ polysilicon 22 to be used as a base lead-out electrode and a CVD oxide film 23 are sequentially grown on the entire surface of the N-type epitaxial layer 20 and LOCOS film 21. Consequently, the CVD oxide film 23 and then P+ polysilicon 22 are selectively removed by etching, using the photoresist by photolithography as the mask, and an intrinsic base region 24 on the surface of the N-type epitaxial layer 20 is exposed.
Furthermore, as shown in FIG. 3(b), after growing a nitride film 25 on the entire surface of the CVD oxide film 23 and intrinsic base region 24, impurities are diffused into the N-type epitaxial layer 20 from the P+ polysilicon 22 by heat treatment, thereby forming a P-type extrinsic base layer 26. Afterwards, using the P+ polysilicon 22 and CVD oxide film 23 as the mask, P-type impurity ions are implanted into the intrinsic base region 24, and a P-type intrinsic base layer 27 is formed.
Next, as shown in FIG. 3(c), the polysilicon grown on the entire surface of the nitride film 25 is anisotropically etched, and a polysilicon side wall 28 is formed. Using this polysilicon side wall 28 as the mask, the nitride film 25 other than the side wall of the P+ polysilicon base, electrode 22 and the peripheral part 29 of the intrinsic base region 24 is etched, and an emitter lead-out part hole 30 is self-aligned to the P+ polysilicon base electrode 22.
Finally, as shown in FIG. 3(d), the N+ polysilicon grown on the entire surface of the CVD oxide film 23 and intrinsic base region 24 is selectively etched by using the photoresist by photolithography as the mask, and an emitter electrode 31 is formed, and N-type impurities are diffused into the N-type epitaxial layer 20 from the N+ polysilicon emitter electrode 31 through the emitter lead-out part hole 30 by heat treatment, thereby forming an N-type emitter layer 32.
According to this manufacturing method of a semiconductor device, all of the extrinsic base region, emitter region, base electrode lead-out part and emitter electrode lead-out part can be formed by a self-aligned process, and the bipolar transistor may be reduced in dimensions and increased raised in speed.
In this prior art, using the P+ polysilicon base electrode 22 as the mask, P-type impurity ions are implanted into the intrinsic base region 24 to form the P-type intrinsic base layer 27. When forming the intrinsic base layer 27 by ion implantation, the junction depth of the intrinsic base layer 27 cannot be set less than 0.2 .mu.m due to channeling at the time of ion implantation. If the intrinsic base layer 27 is deep, the transistor cut-off frequency becomes lowered, which is disadvantageous for raising the operating speed of the bipolar transistor. In the prior art, channeling is decreased by inclining the tilt angle by about 7 degrees to vertical to the semiconductor substrate at the time of ion implantation, but when the tilt angle is inclined, as shown in FIG. 3(b) the tilt pass is shaded by the P+ polysilicon base lead-out electrode 22, and the overlap quantity does not become uniform between the outer marginal part of the intrinsic base layer 27 and the inner marginal part of the extrinsic base layer 26 surrounding the intrinsic base layer 27. As a result, the leakage current between collector and emitter increases in the insufficient overlap portion, or the base resistance increases to induce a reduction of the high frequency characteristics.
Or, when the intrinsic base layer 27 is formed on the entire base region before the step of forming the polysilicon base lead-out electrode 22 and extrinsic base layer 26, the insufficient overlap of the extrinsic base layer 26 and intrinsic base layer 27 may be avoided. In this case, however, by the heat treatment in the step of forming the extrinsic base layer 26, the intrinsic base layer 27 becomes deeper, which also leads to a lowering of the high frequency characteristics.